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?2015 ds20005008b 08/15 not recommended for new designs www.microchip.com 64 mbit (x16) multi-purpose flash plus sst39vf6401b / sst39vf6402b features ? organized as 4m x16 ? single voltage read and write operations ? 2.7-3.6v ? superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention ? low power consumption (typical values at 5 mhz) ? active current: 9 ma (typical) ? standby current: 3 a (typical) ? auto low power mode: 3 a (typical) ? hardware block-prot ection/wp# input pin ? top block-protection (top 32 kword) for sst39vf6402b ? bottom block-protection (bottom 32 kword) for sst39vf6401b ? sector-erase capability ? uniform 2 kword sectors ? block-erase capability ? uniform 32 kword blocks ? chip-erase capability ? erase-suspend/erase-resume capabilities ? hardware reset pin (rst#) ? security-id feature ? microchip: 128 bits; user: 128 bits ? fast read access time: ?70 ns ? latched address and data ? fast erase and word-program: ? sector-erase time: 18 ms (typical) ? block-erase time: 18 ms (typical) ? chip-erase time: 40 ms (typical) ? word-program time: 7 s (typical) ? automatic write timing ? internal v pp generation ? end-of-write detection ? toggle bits ? data# polling ? cmos i/o compatibility ? jedec standard ? flash eeprom pin assignments ? software command sequence compatibility - address format is 11 bits, a 10 -a 0 - block-erase 6th bus write cycle is 30h - sector-erase 6th bus write cycle is 50h ? packages available ? 48-lead tsop (12mm x 20mm) ? 48-ball tfbga (8mm x 10mm) ? all devices are rohs compliant the sst39vf6401b / sst39vf6402b devices are 4m x16, cmos multi-purpose flash plus (mpf+) manufactured with proprietary, high performance cmos superflash technology. the split-gate ce ll design and thick-oxide tunneling injec- tor attain better reliability and manufac turability compared with alternate approaches. the sst39vf6401b / sst3 9vf6402b write (program or erase) with a 2.7-3.6v power supply. these de vices conform to jedec standard pinouts for x16 memories and are command set compatible with other flash devices, enabling customers to save time and resources in implementation. not recommended for new designs. please use sst38vf6401 b/6402b/6403b/64040b
?2015 ds20005008b 08/15 2 64 mbit multi-purpose flash plus sst39vf6401b / sst39vf6402b not recommended for new designs product description the sst39vf640xb devices are 4m x16 cmos multi-purpose flash plus (mpf+) manufactured with proprietary, high-performance cmos superflash technology. the split-gate cell design and thick- oxide tunneling injector attain better reliability and manufa cturability compared with alternate approaches. the sst39vf640xb write (program or erase) with a 2.7-3.6v power supply. these devices conform to jedec standard pin assignments for x16 memories. featuring high performance word-program, the sst39vf640xb devices provide a typical word-pro- gram time of 7 sec. these device s use toggle bit or data# polling to indicate the completion of pro- gram operation. to protect against inadvertent write, they have on-chip hardware and software data protection schemes. designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed typical endurance of 100,000 cycles. data retention is rated at greater than 100 years. the sst39vf640xb devices are suited for applications that require convenient and economical updat- ing of program, configuration, or data memory. for all system applications, they significantly improve performance and reliability, while lo wering power consumption. they inherently use less energy during erase and program than alternative flash technologies. the total energy consumed is a function of the applied voltage, current, and time of application. since for any given voltage range, the superflash technology uses less current to program and ha s a shorter erase time, the total energy consumed during any erase or program operation is less than alternative flash technologies. these devices also improve flexibility while lowering th e cost for program, data, and co nfiguration stora ge applications. the superflash technology provides fixed erase and program times, independent of the number of erase/program cycles that have occurred. therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose erase and pro- gram times increase with accumulated erase/program cycles. to meet high-density, surface mount requirements, the sst39vf640xb devices are offered in 48-lead tsop and 48-ball tfbga packages. see figures and 2 for pin assignments.
?2015 ds20005008b 08/15 3 64 mbit multi-purpose flash plus sst39vf6401b / sst39vf6402b not recommended for new designs block diagram figure 1: block diagram y-decoder i/o buffers and data latches 1288 b1.0 address buffer & latches x-decoder dq 15 - dq 0 memory address oe# ce# we# superflash memory control logic wp# reset#
?2015 ds20005008b 08/15 4 64 mbit multi-purpose flash plus sst39vf6401b / sst39vf6402b not recommended for new designs pin assignments pin assignments for 48-lead tsop figure 2: pin assignments for 48-ball tfbga a15 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# rst# a21 wp# nc a18 a17 a7 a6 a5 a4 a3 a2 a1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a16 nc v ss dq15 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v dd dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe# v ss ce# a0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1288 48-tsop p1.0 standard pinout top view die up 1288 4-tfbga b1k p2.0 a b c d e f g h 6 5 4 3 2 1 top view (balls facing down) a13 a9 we# nc a7 a3 a12 a8 rst# wp# a17 a4 a14 a10 a21 a18 a6 a2 a15 a11 a19 a20 a5 a1 a16 dq7 dq5 dq2 dq0 a0 nc dq14 dq12 dq10 dq8 ce# dq15 dq13 v dd dq11 dq9 oe# v ss dq6 dq4 dq3 dq1 v ss
?2015 ds20005008b 08/15 5 64 mbit multi-purpose flash plus sst39vf6401b / sst39vf6402b not recommended for new designs table 1: pin description symbol pin name functions a ms 1 -a 0 1. a ms = most significant address a ms = a 21 for sst39vf640xb address inputs to provide memory addresses. during sector-erase a ms -a 11 address lines will select the sector. during block-erase a ms -a 15 address lines will select the block. dq 15 -dq 0 data input/output to output data during read cycles and receive input data during write cycles. data is internally latched during a write cycle. the outputs are in tri-state when oe# or ce# is high. wp# write protect to protect t he top/bottom boot block from erase/program operation when grounded. rst# reset to reset and return the device to read mode. ce# chip enable to activate the device when ce# is low. oe# output enable to gate the data output buffers. we# write enable to control the write operations. v dd power supply to provide power supply voltage: 2.7-3.6v v ss ground nc no connection unconnected pins. t1.0 25008
?2015 ds20005008b 08/15 6 64 mbit multi-purpose flash plus sst39vf6401b / sst39vf6402b not recommended for new designs device operation commands are used to initiate the memory operation functions of the device. commands are written to the device using standard microprocessor write sequences. a command is written by asserting we# low while keeping ce# low. the address bus is latched on the falling edge of we# or ce#, whichever occurs last. the data bus is latched on the rising edge of we# or ce#, whichever occurs first. the sst39vf640xb also have the auto low power mode which puts the device in a near standby mode after data has been accessed with a valid read operation. this reduces the i dd active read cur- rent from typically 9 ma to typically 3 a. the auto low power mode reduces the typical i dd active read current to the range of 2 ma/mhz of read cycle time. the device exits the auto low power mode with any address transition or control signal transition used to initiate another read cycle, with no access time penalty. note that the device does not enter auto-low power mode after power-up with ce# held steadily low, until the first address transition or ce# is driven high. read the read operation of the sst39vf640xb is controlled by ce# and oe#, both have to be low for the system to obtain data from the outputs. ce# is used for device selection. when ce# is high, the chip is deselected and only standby power is consumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either ce# or oe# is high. refer to the read cycle timing diagram for further details (figure 3). word-program operation the sst39vf640xb are programmed on a word-by-word basis. before programming, the sector where the word exists must be fully erased. the program operation is accomplished in three steps. the first step is the three-byte load sequence for software data protection. the second step is to load word address and word data. during the word-program operation, the addresses are latched on the falling edge of either ce# or we#, whichever occurs last. the data is latc hed on the rising edge of either ce# or we#, whichever occurs first. the third step is the internal program operation which is ini- tiated after the rising edge of the fourth we# or ce#, whichever occurs first. the program operation, once initiated, will be co mpleted within 10 s. see figures 4 and 5 for we# and ce# controlled pro- gram operation timing diagrams and figure 19 for flowcharts. during the program operation, the only valid reads are data# polling and toggle bit. during the internal program operation, the host is free to perform additional tasks. any commands issued during the internal program operation are ignored. during the command sequence, wp# should be statically held high or low. sector/block-erase operation the sector- (or block-) erase operation allows the system to erase the device on a sector-by-sector (or block-by-block) basis. the sst39vf640xb offer both sector-erase and block-erase mode. the sector architecture is based on uniform sector size of 2 kword. the block-erase mode is based on uniform block size of 32 kword. the sector-erase operation is initiated by executing a six-byte command sequence with sector-erase command (50h) and sector address (sa) in the last bus cycle. the block- erase operation is initiated by executing a six-byte command sequence with block-erase command (30h) and block address (ba) in the last bus cycle. the sector or block address is latched on the falling edge of the sixth we# pulse, while the command (50h or 30h) is latched on the rising edge of the sixth we# pulse. the internal erase operation begins after the sixth we# pulse. the end-of-erase opera- tion can be determined us ing either data# polling or toggle bi t methods. see figures 9 and 10 for tim-
?2015 ds20005008b 08/15 7 64 mbit multi-purpose flash plus sst39vf6401b / sst39vf6402b not recommended for new designs ing waveforms and figure 23 for the flowchart. any commands issued during the sector- or block- erase operation are ignored. when wp# is low, any attempt to sector- (block-) erase the protected block will be ignored. during the command sequence, wp# should be statically held high or low. erase-suspend/erase-resume commands the erase-suspend operation temporarily suspends a sector- or block-erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an erase operation. the operation is executed by issuing one byte command sequence with erase- suspend command (b0h). the device automatically en ters read mode typically within 20 s after the erase-suspend command had been issued. valid data can be read from any sector or block that is not suspended from an erase operation. reading at address location within erase-suspended sectors/ blocks will output dq 2 toggling and dq 6 at ?1?. while in erase-suspend mode, a word-program oper- ation is allowed except for the sector or block selected for erase-suspend. to resume sector-erase or block-erase operation which has been suspended the system must issue erase resume command. the operation is executed by issuing one byte command sequence with erase resume command (30h) at any address in the last byte sequence. chip-erase operation the sst39vf640xb provide a chip-erase operation, which allows the user to erase the entire mem- ory array to the ?1? state. this is useful when the entire device must be quickly erased. the chip-erase operation is init iated by executing a six-byte command sequence with chip-erase command (10h) at address 555h in the last byte sequence. the erase operation begins with the rising edge of the sixth we# or ce#, whichever occurs first. during the erase operation, the only valid read is toggle bit or data# polling. see table 6 for the co mmand sequence, fi gure 9 for timing diagram, and figure 23 for the flowchart. any commands issued during the chip-erase operation are ignored. when wp# is low, any attempt to chip-erase will be i gnored. during the comma nd sequence, wp# should be statically held high or low. write operation status detection the sst39vf640xb provide two software means to detect the completion of a write (program or erase) cycle, in order to optimize the system write cycle time. the software detection includes two sta- tus bits: data# polling (dq 7 ) and toggle bit (dq 6 ). the end-of-write detection mode is enabled after the rising edge of we#, which initiates the internal program or erase operation. the actual completion of the nonvolatile write is asynchronous with the system; therefore, either a data# polling or toggle bit read may be simultaneous with the completion of th e write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either dq 7 or dq 6 . in order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the wr ite cycle, otherwise the rejection is valid.
?2015 ds20005008b 08/15 8 64 mbit multi-purpose flash plus sst39vf6401b / sst39vf6402b not recommended for new designs data# polling (dq 7 ) when the sst39vf640xb are in the internal program operation, any attempt to read dq 7 will produce the complement of the true data. once the program operation is completed, dq 7 will produce true data. note that even though dq 7 may have valid data immediately following the completion of an internal write operation, the remaining data outputs may still be invalid: valid data on the entire dat a bus will appear in subse- quent successive read cycles after an interval of 1 s. during internal erase operation, any attempt to read dq 7 will produce a ?0?. once the internal erase oper ation is completed, dq 7 will produce a ?1?. the data# polling is valid after the rising edge of four th we# (or ce#) pulse for program operation. for sector-, block- or chip-erase, the data# polling is valid after the rising edge of sixth we# (or ce#) pulse. see figure 6 for data# polling timing diagram and figure 20 for a flowchart. toggle bits (dq6 and dq2) during the internal program or erase operation, any consecutive attempts to read dq 6 will produce alternating ?1?s and ?0?s, i.e., toggling between 1 and 0. when the internal program or erase operation is completed, the dq 6 bit will stop toggling. the device is then ready for the next op eration. for sector- , block-, or chip-erase, the toggle bit (dq 6 ) is valid after the rising edge of sixth we# (or ce#) pulse. dq 6 will be set to ?1? if a read op eration is attempted on an eras e-suspended sector/block. if pro- gram operation is initiated in a sector/block not selected in erase-suspend mode, dq 6 will toggle. an additional toggle bit is available on dq 2 , which can be used in conjunction with dq 6 to check whether a particular sector is being actively eras ed or erase-suspended. table 2 shows detailed status bits information. the toggle bit (dq 2 ) is valid after the rising edge of the last we# (or ce#) pulse of write operation. see figure 7 for toggle bit timing diagram and figure 20 for a flowchart. note: dq 7 and dq 2 require a valid address when reading status information. table 2: write operation status status dq 7 dq 6 dq 2 normal operation standard program dq 7 # toggle no toggle standard erase 0 toggle toggle erase-suspend mode read from erase-suspended sector/block 1 1 toggle read from non- erase-suspended sector/block data data data program dq 7 # toggle n/a t2.0 25008
?2015 ds20005008b 08/15 9 64 mbit multi-purpose flash plus sst39vf6401b / sst39vf6402b not recommended for new designs data protection the sst39vf640xb provide both hardware and software features to protect nonvolatile data from inadvertent writes. hardware data protection noise/glitch protection: a we# or ce# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection: the write operation is inhibited when v dd is less than 1.5v. write inhibit mode: forcing oe# low, ce# high, or we# high will inhibit the write operation. this pre- vents inadvertent writes during power-up or power-down. hardware block protection the sst39vf6402b support top hardware block protection, which protects the top 32 kword block of the device. the sst39vf6401b support bottom hardware block protection, which protects the bottom 32 kword block of the device. the boot block address ranges are described in table 3. program and erase operations are prevented on the 32 kword when wp# is low. if wp# is left floating, it is internally held high via a pull-up resistor, and the boot block is unprotected, enabling program and erase opera- tions on that block. table 3: boot block address ranges product address range bottom boot block sst39vf6401b 000000h-007fffh top boot block sst39vf6402b 3f8000h-3fffffh t3.0 25008
?2015 ds20005008b 08/15 10 64 mbit multi-purpose flash plus sst39vf6401b / sst39vf6402b not recommended for new designs hardware reset (rst#) the rst# pin provides a hardware method of resetting the device to read array data. when the rst# pin is held low for at least t rp, any in-progress operation will termin ate and return to read mode. when no internal program/erase operation is in progress, a minimum period of t rhr is required after rst# is driven high before a valid read can take place (see figure 15). the erase or program operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity. software data protection (sdp) the sst39vf640xb provide the jedec approved software data protection scheme for all data alter- ation operations, i.e., program and erase. any program operation requires the inclusion of the three- byte sequence. the three-byte load sequence is used to initiate the program operation, providing opti- mal protection from inadvertent write operations, e.g., during the system power-up or power-down. any erase operation requires the inclusion of six-byte sequence. these devices are shipped with the software data protection permanently enabled. see table 6 for the specific software command codes. during sdp command sequence, in valid commands will abort the devi ce to read mode within t rc. the contents of dq 15 -dq 8 can be v il or v ih , but no other value, during any sdp command sequence. common flash memory interface (cfi) the sst39vf640xb also contain the cfi information to describe the characteristics of the device. in order to enter the cfi query mode, the system must write three-byte sequence, same as product id entry command with 98h (cfi query command) to address 555h in the last byte sequence. once the device enters the cfi query mode, the system can read cfi data at the addresses given in tables 7 through 9. the system must write the cfi exit command to return to read mode from the cfi query mode.
?2015 ds20005008b 08/15 11 64 mbit multi-purpose flash plus sst39vf6401b / sst39vf6402b not recommended for new designs product identification the product identification mode identifies the devices as the sst39vf6401b and sst39vf6402b, and the manufacturer as sst. this mode may be accessed through software operations. users may use the software product identification operation to identify the part (i.e., using the device id) when using multiple manufacturers in the same socket. for details, see table 6 for software operation, figure 11 for the software id entry and read timing diagram and figure 21 for the software id entry com- mand sequence flowchart. product identification mode exit/cfi mode exit in order to return to the standard read mode, the software product identification mode must be exited. exit is accomplished by issuing the software id exit command sequence, which returns the device to the read mode. this command may also be used to reset the device to the read mode after any inad- vertent transient condition that apparently causes the device to behave abnormally, e.g., not read cor- rectly. please note that the software id exit/cfi exit command is ignored during an internal program or erase operation. see table 6 for software command codes, figure 13 for timing waveform, and fig- ures 21 and 22 for flowcharts. table 4: product identification address data manufacturer?s id 0000h bfh device id sst39vf6401b 0001h 236dh sst39vf6402b 0001h 236ch t4.0 25008
?2015 ds20005008b 08/15 12 64 mbit multi-purpose flash plus sst39vf6401b / sst39vf6402b not recommended for new designs security id the sst39vf640xb devices offer a 256-bit security id space. the secure id space is divided into two 128-bit segments - one factory programmed segment and one user programmed segment. the first segment is programmed and locked at microchip with a random 128-bit number. the user segment is left un-programmed for the customer to program as desired. to program the user segment of the security id, the user must use the security id word-program command. to detect en d-of-write for the sec id, read the to ggle bits. do not use data# polling. once this is complete, the sec id should be locked using the user sec id program lock-out. this disables any future corruption of this space. note that regardless of whether or not the sec id is locked, neither sec id segment can be erased. the secure id space can be queried by executing a three-byte command sequence with enter sec id command (88h) at address 555h in the last byte sequence. to exit this mode, the exit sec id com- mand should be executed. refer to table 6 for more details.
?2015 ds20005008b 08/15 13 64 mbit multi-purpose flash plus sst39vf6401b / sst39vf6402b not recommended for new designs operations table 5: operation modes selection mode ce# oe# we# dq address read v il v il v ih d out a in program v il v ih v il d in a in erase v il v ih v il x 1 1. x can be v il or v ih , but no other value. sector or block address, xxh for chip-erase standby v ih x x high z x write inhibit x v il x high z/ d out x xxv ih high z/ d out x product identification software mode v il v il v ih see table 6 t5.0 25008 table 6: software command sequence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle addr 1 1. address format a 10 -a 0 (hex). addresses a 11 - a 21 can be v il or v ih, but no other value, for command sequence for sst39vf640xb. data 2 2. dq 15 -dq 8 can be v il or v ih , but no other value, for command sequence addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 word-program 555h aah 2aah 55h 555h a0h wa 3 3. wa = program word address data sector-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa x 4 4. sa x for sector-erase; uses a ms -a 11 address lines ba x , for block-erase; uses a ms -a 15 address lines a ms = most significant address a ms = a 21 for sst39vf640xb 50h block-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h ba x 4 30h chip-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h erase-suspend xxxxh b0h erase-resume xxxxh 30h query sec id 5 5. with a ms -a 4 = 0; sec id is read with a 3 -a 0 , sst id is read with a 3 = 0 (address range = 000000h to 000007h), user id is read with a 3 = 1 (address range = 000010h to 000017h). lock status is read with a 7 -a 0 = 0000ffh. unlocked: dq 3 = 1 / locked: dq 3 = 0. 555h aah 2aah 55h 555h 88h user security id word-program 555h aah 2aah 55h 555h a5h wa 6 6. valid word-addresses for sec id are from 000000h-000007h and 000010h-000017h. data user security id program lock-out 555h aah 2aah 55h 555h 85h xxh 6 0000h software id entry 7,8 555h aah 2aah 55h 555h 90h cfi query entry 555h aah 2aah 55h 555h 98h software id exit 9,10 /cfi exit/sec id exit 555h aah 2aah 55h 555h f0h software id exit 9,10 /cfi exit/sec id exit xxh f0h t6.0 25008
?2015 ds20005008b 08/15 14 64 mbit multi-purpose flash plus sst39vf6401b / sst39vf6402b not recommended for new designs 7. the device does not remain in software product id mode if powered down. 8. with a ms -a 1 =0; manufacturer id = 00bfh, is read with a 0 = 0, sst39vf6401b device id = 236dh, is read with a 0 = 1, sst39vf6402b device id = 236ch, is read with a 0 = 1. a ms = most significant address a ms = a 21 for sst39vf640xb 9. both software id exit operations are equivalent 10. if users never lock after programming, sec id can be pr ogrammed over the previously unprogrammed bits (data=1) using the sec id mode again (the programmed ?0? bits cannot be reversed to ?1?). valid wo rd-addresses for sec id are from 000000h-000007h and 000010h-000017h. table 7: cfi query identification string 1 for sst39vf640xb 1. refer to cfi publication 100 for more details. address data data 10h 0051h query unique ascii string ?qry? 11h 0052h 12h 0059h 13h 0002h primary oem command set 14h 0000h 15h 0000h address for primary extended table 16h 0000h 17h 0000h alternate oem command set (00h = none exists) 18h 0000h 19h 0000h address for alternate oem extended table (00h = none exits) 1ah 0000h t7.0 25008 table 8: system interface information for sst39vf640xb address data data 1bh 0027h v dd min (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1ch 0036h v dd max (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1dh 0000h v pp min. (00h = no v pp pin) 1eh 0000h v pp max. (00h = no v pp pin) 1fh 0003h typical time out for word-program 2 n s (2 3 = 8 s) 20h 0000h typical time out for min. size buffer program 2 n s (00h = not supported) 21h 0004h typical time out for individual sector/block-erase 2 n ms (2 4 = 16 ms) 22h 0005h typical time out for chip-erase 2 n ms (2 5 = 32 ms) 23h 0001h maximum time out for word-program 2 n times typical (2 1 x 2 3 = 16 s) 24h 0000h maximum time out for buffer program 2 n times typical 25h 0001h maximum time out for individual sector/block-erase 2 n times typical (2 1 x 2 4 = 32 ms) 26h 0001h maximum time out for chip-erase 2 n times typical (2 1 x 2 5 = 64 ms) t8.0 25008
?2015 ds20005008b 08/15 15 64 mbit multi-purpose flash plus sst39vf6401b / sst39vf6402b not recommended for new designs table 9: device geometry information for sst39vf640xb address data data 27h 0017h device size = 2 n bytes (17h = 23; 2 23 = 8 mbyte) 28h 0001h flash device interface description; 0001h = x16-only asynchronous interface 29h 0000h 2ah 0000h maximum number of bytes in multi-byte write = 2 n (00h = not supported) 2bh 0000h 2ch 0002h number of erase sector/block sizes supported by device 2dh 00ffh sector information (y + 1 = number of sectors; z x 256b = sector size) 2eh 0007h y = 2047 + 1 = 2048 sectors (07ffh = 2047) 2fh 0010h 30h 0000h z = 16 x 256 bytes = 4 kbytes/sector (0010h = 16) 31h 007fh block information (y + 1 = number of blocks; z x 256b = block size) 32h 0000h y =127 + 1 = 128 blocks (007fh = 127) 33h 0000h 34h 0001h z = 256 x 256 bytes = 64 kbytes/block (0100h = 256) t9.0 25008
?2015 ds20005008b 08/15 16 64 mbit multi-purpose flash plus sst39vf6401b / sst39vf6402b not recommended for new designs absolute maximum stress ratings (applied conditions greater than those listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating con- ditions may affect device reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +12 5c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to + 150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . -2.0v to v dd +2.0v voltage on a 9 pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 13.2v package power dissipation capability (t a = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount solder reflow temperature 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c for 10 seconds output short circuit current 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. excluding certain with-pb 32- plcc units, all packages are 260 c capable in both non-pb and with-pb solder versions. certain with-pb 32-plcc package types are capable of 240 c for 10 seconds; please consult the factory for the latest information. 2. outputs shorted for no more than one second. no more than one output shorted at a time. table 10: operating range range ambient temp v dd commercial 0c to +70c 2.7-3.6v industrial -40c to +85c 2.7-3.6v t10.1 25008 table 11: ac conditions of test 1 1. see figures 17 and 18 input rise/fall time output load 5ns c l = 30 pf t11.1 25008
?2015 ds20005008b 08/15 17 64 mbit multi-purpose flash plus sst39vf6401b / sst39vf6402b not recommended for new designs table 12: dc operating characteristics v dd = 2.7-3.6v 1 symbol parameter limits test conditions min max units i dd power supply current address input=v ilt /v iht 2 , at f=5 mhz, v dd =v dd max read 3 18 ma ce#=v il , oe#=we#=v ih , all i/os open program and erase 35 ma ce#=we#=v il , oe#=v ih i sb standby v dd current 20 a ce#=v ihc , v dd =v dd max i alp auto low power 20 a ce#=v ilc , v dd =v dd max all inputs=v ss or v dd, we#=v ihc i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i liw input leakage current on wp# pin and rst# 10 a wp#=gnd to v dd or rst#=gnd to v dd i lo output leakage current 10 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ilc input low voltage (cmos) 0.3 v v dd =v dd max v ih input high voltage 0.7v dd vv dd =v dd max v ihc input high voltage (cmos) v dd -0.3 v v dd =v dd max v ol output low voltage 0.2 v i ol =100 a, v dd =v dd min v oh output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min t12.0 25008 1. typical conditions for the active current shown on the front page of the data sheet are average values at 25c (room temperature), and v dd = 3v. not 100% tested. 2. see figure 17 3. the i dd current listed is typically less than 2ma/mhz, with oe# at v ih. ty p i c a l v dd is 3v. table 13: recommended system power-up timings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for in itial qualification and after a design or process change that could affect this paramet er. power-up to read operation 100 s t pu-write 1 power-up to program/erase operation 100 s t13.0 25008 table 14: capacitance (t a = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for in itial qualification and after a design or process change that could affect this paramet er. i/o pin capacitance v i/o = 0v 12 pf c in 1 input capacitance v in = 0v 6 pf t14.0 25008 table 15: reliability characteristics symbol parameter minimum specification units test method n end 1,2 1. this parameter is measured only for in itial qualification and after a design or process change that could affect this paramet er. 2. n end endurance rating is qualified as a 10,000 cycle minimum for the whole device. a sector- or block-level rating would result in a higher minimum specification. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t15.0 25008
?2015 ds20005008b 08/15 18 64 mbit multi-purpose flash plus sst39vf6401b / sst39vf6402b not recommended for new designs ac characteristics table 16: read cycle timing parameters v dd = 2.7-3.6v symbol parameter sst39vf640xb-70 units min max t rc read cycle time 70 ns t ce chip enable access time 70 ns t aa address access time 70 ns t oe output enable access time 35 ns t clz 1 1. this parameter is measured only for initial qualification and after a desig n or process change that could affect this parameter. ce# low to active output 0 ns t olz 1 oe# low to active output 0 ns t chz 1 ce# high to high-z output 20 ns t ohz 1 oe# high to high-z output 20 ns t oh 1 output hold from address change 0 ns t rp 1 rst# pulse width 500 ns t rhr 1 rst# high before read 50 ns t ry 1,2 2. this parameter applies to sector-erase, block-erase, and program operations. this parameter does not apply to chip-erase operations. rst# pin low to read mode 20 s t16.0 25008 table 17: program/erase cycle timing parameters symbol parameter min max units t bp word-program time 10 s t as address setup time 0 ns t ah address hold time 30 ns t cs we# and ce# setup time 0 ns t ch we# and ce# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 10 ns t cp ce# pulse width 40 ns t wp we# pulse width 40 ns t wph 1 1. this parameter is measured only for initial qualification and after a desig n or process change that could affect this parameter. we# pulse width high 30 ns t cph 1 ce# pulse width high 30 ns t ds data setup time 30 ns t dh 1 data hold time 0 ns t ida 1 software id access and exit time 150 ns t se sector-erase 25 ms t be block-erase 25 ms t sce chip-erase 50 ms t17.0 25008
?2015 ds20005008b 08/15 19 64 mbit multi-purpose flash plus sst39vf6401b / sst39vf6402b not recommended for new designs figure 3: read cycle timing diagram figure 4: we# controlled program cycle timing diagram 1288 f03.0 address a ms-0 dq 15-0 we# oe# ce# t ce t rc t aa t oe t olz v ih high-z t clz t oh t chz high-z data valid data valid t ohz note: a ms = most significant address a ms = a 21 for sst39vf640xb 1288 f04.0 address a ms-0 dq 15-0 t dh t wph t ds t wp t ah t as t ch t cs ce# sw0 sw1 sw2 555 2aa 555 addr xxaa xx55 xxa0 data internal program operation starts word (addr/data) oe# we# t bp note: a ms = most significant address a ms = a 21 for sst39vf640xb wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value.
?2015 ds20005008b 08/15 20 64 mbit multi-purpose flash plus sst39vf6401b / sst39vf6402b not recommended for new designs figure 5: ce# controlled program cycle timing diagram figure 6: data# polling timing diagram 1288 f05.0 address a ms-0 dq 15-0 t dh t cph t ds t cp t ah t as t ch t cs we# sw0 sw1 sw2 555 2aa 555 addr xxaa xx55 xxa0 data internal program operation starts word (addr/data) oe# ce# t bp note: a ms = most significant address a ms = a 21 for sst39vf640xb wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value. 1288 f06.0 address a ms-0 dq 7 data data # data # data we# oe# ce# t oeh t oe t ce t oes note: a ms = most significant address a ms = a 21 for sst39vf640xb
?2015 ds20005008b 08/15 21 64 mbit multi-purpose flash plus sst39vf6401b / sst39vf6402b not recommended for new designs figure 7: toggle bits timing diagram figure 8: we# controlled chip-erase timing diagram 1288 f07.0 address a ms-0 dq 6 and dq 2 we# oe# ce# t oe t oeh t ce t oes two read cycles with same outputs note: a ms = most significant address a ms = a 21 for sst39vf640xb 1288 f08.0 address a ms-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 555 2aa 2aa 555 555 xx55 xx10 xx55 xxaa xx80 xxaa 555 oe# ce# six-byte code for chip-erase t sce t wp note: this device also supports ce# controlled ch ip-erase operation the we# and ce# signals are interchangeable as long as minimum timings are met. (see table 17) a ms = most significant address a ms = a 21 for sst39vf640xb wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value.
?2015 ds20005008b 08/15 22 64 mbit multi-purpose flash plus sst39vf6401b / sst39vf6402b not recommended for new designs figure 9: we# controlled block-erase timing diagram 1288 f09.0 address a ms-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 555 2aa 2aa 555 555 xx55 xx30 xx55 xxaa xx80 xxaa ba x oe# ce# six-byte code for block-erase t be t wp note: this device also supports ce# controlled bl ock-erase operation the we# and ce# signals are interchangeable as long as minimu m timings are met. (see table 17) ba x = block address a ms = most significant address a ms = a 21 for sst39vf640xb wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value.
?2015 ds20005008b 08/15 23 64 mbit multi-purpose flash plus sst39vf6401b / sst39vf6402b not recommended for new designs figure 10: we# controlled sector-erase timing diagram 1288 f10.0 address a ms-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 555 2aa 2aa 555 555 xx55 xx50 xx55 xxaa xx80 xxaa sa x oe# ce# six-byte code for sector-erase t se t wp note: this device also supports ce# controlled se ctor-erase operation the we# and ce# signals are interchangeable as long as minimu m timings are met. (see table 17) sa x = sector address a ms = most significant address a ms = a 21 for sst39vf640xb wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value.
?2015 ds20005008b 08/15 24 64 mbit multi-purpose flash plus sst39vf6401b / sst39vf6402b not recommended for new designs figure 11: software id entry and read figure 12: cfi query entry and read 1288 f11.0 address a 14-0 t ida dq 15-0 we# sw0 sw1 sw2 555 2aa 555 0000 0001 oe# ce# three-byte sequence for software id entry t wp t wph t aa 00bf device id xx55 xxaa xx90 note: device id = 236dh for sst39vf6401b and 236ch for sst39vf6402b wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value. 1288 f12.0 address a 14-0 t ida dq 15-0 we# sw0 sw1 sw2 555 2aa 555 oe# ce# three-byte sequence for cfi query entry t wp t wph t aa xx55 xxaa xx98 note: wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value.
?2015 ds20005008b 08/15 25 64 mbit multi-purpose flash plus sst39vf6401b / sst39vf6402b not recommended for new designs figure 13: software id exit/cfi exit figure 14: sec id entry 1288 f13.0 address a 14-0 dq 15-0 t ida t wp t whp we# sw0 sw1 sw2 555 2aa 555 three-byte sequence for software id exit and reset oe# ce# xxaa xx55 xxf0 note: wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value. 1288 f14.0 address a ms-0 t ida dq 15-0 we# sw0 sw1 sw2 555 2aa 555 oe# ce# three-byte sequence for cfi query entry t wp t wph t aa xx55 xxaa xx88 note: a ms = most significant address a ms = a 21 for sst39vf640xb wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value.
?2015 ds20005008b 08/15 26 64 mbit multi-purpose flash plus sst39vf6401b / sst39vf6402b not recommended for new designs figure 15: rst# timing diagram (when no internal operation is in progress) figure 16: rst# timing diagram (during program or erase operation) 1288 f15.0 rst# ce#/oe# t rp t rhr 1288 f16.0 rst# ce#/oe# t rp t ry end-of-write detection (toggle-bit)
?2015 ds20005008b 08/15 27 64 mbit multi-purpose flash plus sst39vf6401b / sst39vf6402b not recommended for new designs figure 17: ac input/output reference waveforms figure 18: a test load example 1288 f17.0 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (0.9 v dd ) for a logic ?1? and v ilt (0.1 v dd ) for a logic ?0?. measurement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test 1288 f18.0 to tester to dut c l
?2015 ds20005008b 08/15 28 64 mbit multi-purpose flash plus sst39vf6401b / sst39vf6402b not recommended for new designs figure 19: word-program algorithm 1288 f19.0 start load data: xxaah address: 555h load data: xx55h address: 2aah load data: xxa0h address: 555h load word address/word data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed x can be v il or v ih , but no other value
?2015 ds20005008b 08/15 29 64 mbit multi-purpose flash plus sst39vf6401b / sst39vf6402b not recommended for new designs figure 20: wait options 1288 f20.0 wait t bp , t sce, t se or t be program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match? read same word data# polling program/erase completed program/erase completed read word is dq 7 = true data? read dq 7 program/erase initiated program/erase initiated
?2015 ds20005008b 08/15 30 64 mbit multi-purpose flash plus sst39vf6401b / sst39vf6402b not recommended for new designs figure 21: software id/cfi entry command flowcharts 1288 f21.0 load data: xxaah address: 555h software product id entry command sequence load data: xx55h address: 2aah load data: xx90h address: 555h wait t ida read software id load data: xxaah address: 555h cfi query entry command sequence load data: xx55h address: 2aah load data: xx98h address: 555h wait t ida read cfi data load data: xxaah address: 555h sec id query entry command sequence load data: xx55h address: 2aah load data: xx88h address: 555h wait t ida read sec id x can be v il or v ih , but no other value
?2015 ds20005008b 08/15 31 64 mbit multi-purpose flash plus sst39vf6401b / sst39vf6402b not recommended for new designs figure 22: software id/cfi exit command flowcharts 1288 f22.0 load data: xxaah address: 555h software id exit/cfi exit/sec id exit command sequence load data: xx55h address: 2aah load data: xxf0h address: 555h load data: xxf0h address: xxh return to normal operation wait t ida wait t ida return to normal operation x can be v il or v ih , but no other value
?2015 ds20005008b 08/15 32 64 mbit multi-purpose flash plus sst39vf6401b / sst39vf6402b not recommended for new designs figure 23: erase command sequence 1288 f23.0 load data: xxaah address: 555h chip-erase command sequence load data: xx55h address: 2aah load data: xx80h address: 555h load data: xx55h address: 2aah load data: xx10h address: 555h load data: xxaah address: 555h wait t sce chip erased to ffffh load data: xxaah address: 555h sector-erase command sequence load data: xx55h address: 2aah load data: xx80h address: 555h load data: xx55h address: 2aah load data: xx50h address: sa x load data: xxaah address: 555h wait t se sector erased to ffffh load data: xxaah address: 555h block-erase command sequence load data: xx55h address: 2aah load data: xx80h address: 555h load data: xx55h address: 2aah load data: xx30h address: ba x load data: xxaah address: 555h wait t be block erased to ffffh x can be v il or v ih , but no other value
?2015 ds20005008b 08/15 33 64 mbit multi-purpose flash plus sst39vf6401b / sst39vf6402b not recommended for new designs product ordering information valid combinati ons for sst39vf6401b SST39VF6401B-70-4C-EKE sst39vf6401b-70-4c-b1ke sst39vf6401b-70-4i-eke sst39vf6401b-70-4i-b1ke valid combinati ons for sst39vf6402b sst39vf6402b-70-4c-eke sst39vf6402b-70-4c-b1ke sst39vf6402b-70-4i-eke sst39vf6402b-70-4i-b1ke note: valid combinations are those products in mass producti on or will be in mass production. consult your sst sales representative to confirm availability of valid co mbinations and to determine availability of new combi- nations. sst 39 vf 6401b - 70 - 4i - qae xx x x xxxx x-xx -xx - xxx environmental attribute e 1 = non-pb package modifier k = 48 balls or leads package type e = tsop (type1, die up, 12mm x 20mm) b1 = tfbga (8mm x 10mm, 0.8mm pitch) temperature range c = commercial = 0c to +70c i = industrial = -40c to +85c minimum endurance 4 = 10,000 cycles read access speed 70 = 70 ns hardware block protection 1 = bottom boot-block 2 = top boot-block device density 640 = 64 mbit voltage v = 2.7-3.6v product series 39 = multi-purpose flash plus 1. environmental suffix ?e? denotes non-pb solder. non-pb solder devices are ?rohs compliant?.
?2015 ds20005008b 08/15 34 64 mbit multi-purpose flash plus sst39vf6401b / sst39vf6402b not recommended for new designs packaging diagrams figure 24: 48-lead thin small outline package (tsop) 12mm x 20mm package code: ek for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: microchip technology drawing c04-14036a sheet 1 of 1 48-lead thin small outline package (eke/f) - [tsop] 48-tsop-ek-8 note: 1. complies with je dec publication 95 mo-142 dd dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (max/min). 3. coplanarity: 0.1 mm 4. maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
?2015 ds20005008b 08/15 35 64 mbit multi-purpose flash plus sst39vf6401b / sst39vf6402b not recommended for new designs figure 25: 48-ball thin-profile, fine-pitch ba ll grid array (tfbga) 8mm x 10mm package code: b1k for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: microchip technology drawing c04-14034a sheet 1 of 1 48-lead thin fine-pitch ball grid array (b1ke/f) - 8x10 mm body [tfbga] 48-tfbga-b1k-8x10-450mic-5 note: 1. although many dimensions are similar to those of jedec publication 95, mo-210, this specific package is not registered. 2. all linear dimensions ar e in millimeters. 3. coplanarity: 0.12 mm 4. ball opening size is 0.38 mm ( 0.05 mm)
?2015 ds20005008b 08/15 36 64 mbit multi-purpose flash plus sst39vf6401b / sst39vf6402b not recommended for new designs table 18: revision history revision description date 00 ? initial release mar 2005 01 ? clarified jedec software co mmand compatibility on page 1 may 2005 02 ? changed document phase from preliminary information to data sheet jul 2006 a ? removed pb and 90ns parts ? marked the document ?not recommended for new designs? ? applied new document format ? released document under letter revision system ? updated spec number from s71288 to ds25008 aug 2011 b ? updated ?not recommended for new designs? statement on page 1. aug 2015 ? 2015 microchip technology inc. sst, silicon storage technology, the sst logo, superflash, and mtp are registered trademarks of microchip technology, inc. mpf, sqi, serial quad i/o, and z-scale are trademarks of microc hip technology, inc. all other trademarks and registered trade- marks mentioned herein are the property of their respective owners. specifications are subject to change without notice. refer to www.microchip.com for th e most recent documentation. for the most current package drawings, please see the packaging specific ation located at http://www.microchip.com/packaging. memory sizes denote raw storage capacity ; actual usable capacity may be less. microchip makes no warranty for the use of its products other than those expressly contained in the standard terms and conditio ns of sale. for sales office locations and information, please see www.microchip.com. www.microchip.com isbn: 978 \ 1 \ 63277 \ 710 \ 2

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